High throughput and low latency are the desirable characteristics of a multi processing system. CLICHE (ChipLevel Integration of Communicating Heterogeneous Elements) is the simplest form of Network-on-Chip architecture in terms of the layout and the local interconnections between resources and switches. The throughput varies with the number of virtual channels. When the number of virtual channels is increased, the throughput is increased. On the other hand, the average message latency increases with the number of virtual channels. To keep the latency low while preserving the throughput, the number of virtual channels is constrained to certain number. A novel multichannel signal acquisition module is proposed to integrate IP blocks. The proposed module achieves the optimal solution for large number of virtual channels. It reduces the memory requirement and power consumption as well. A Field Programmable Gate Arrays-based prototype is developed to verify the proposed module. Different case studies are studied in this research. As a result, the proposed module can schedule given tasks that are not schedulable via round-robin technique. Even in scenarios that both round-robin and proposed module can successfully schedule the given task, proposed module reduces the amount of data being acquired by 59%, which in turn decreases memory requirements and power consumption as well.
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