Design of a Switched-Capacitor Dc Balancer for Aerospace Applications

摘要

In this paper, a 40 kW interleaved switched-capacitor dc balancer (ISCDCB) is presented. Using FEA (AN-SYS Q3D) and stray impedance reduction techniques, a low impedance bus bar was designed. Simulation and a low power prototype were used to validate the proposed ISCDCB. The balancing response under various loading scenarios from 40 W to 4 kW are shown. Design considerations and improvements for higher power and higher frequency operation are discussed.