In the last years, partial reconfigurable systems (PRSs) have included Networks-on-Chip (NoCs) as their communication structure. The problem of mapping and positioning in NoCs have been extended to PSRs. Mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. The placement problem deals with the allocation of those cores inside the reconfigurable device. Recently, several works have proposed specific and robust NoC architectures for PRSs in which the mapping problem cannot be dissociated from the placement one, but, this problem has not been addressed properly yet. In this paper, the design-time placement and mapping problem for NoCs in reconfigurable architectures is explored and the sensibility of design parameters in respect to the cost function is evaluated.
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