A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2m)

摘要

Computing modular multiplication over GF(2m) is often a performance critical operation in cryptographic applications. This paper describes the architecture of a scalable and configurable Montgomery modular multiplier over binary fields. This architecture, implemented on a FPGA platform, aims to reduce the computation time thanks to the pipelining of the datapath. Scalability is achieved by allowing to change field parameters while keeping the same design. A timing area tradeoff allows to get a significant speedup at a reasonable cost.