UDP/IP stack in FPGA for hard real-time communication of Sonar sensor data

摘要

In modern day Sonar Systems Gigabit Ethernet is used as a communication bus for transfer of sensor data between various embedded processors. Typically UDP/IP protocol with Jumbo frames is used to achieve high throughput. This paper presents the design and implementation of a minimal UDP/IP stack in FPGA that can provide hard real-time transmission of Ethernet frames required in Sonar. The network and transport layers are implemented in the FPGA. The embedded tri-mode Ethernet MAC hard core from Xilinx is configured as the data link layer. The stack is realized on the Virtex-5 FPGA in the Xilinx ML-507 evaluation platform. The module is tested in an Ethernet network for its functionality using a Network Analyzer. Throughput in excess of 900 Mbps has been achieved with minimal and predictable jitter in the Inter Packet Gap and Jumbo frame support meeting the real-time requirements of Sonar systems.