Utilizing 2D and 3D Rectilinear Blocks for Efficient IP Reuse and Floorplanning of 3D-Integrated Systems

摘要

The reuse of predesigned intellectual property (IP) blocks is critical for the commercial success of three-dimensional (3D) electronic circuits. In practice, IP blocks can be specified as rectangular as well as rectilinear 2D blocks. The 3D equivalent of 2D rectilinear blocks, orthogonal polyhedra, may be utilized for modeling tightly interconnected (sub-)modules placed onto adjacent dies or for design automation of versatile 3D-integrated systems. Such complex block geometries have not been adequately considered until now. We propose a new 3D layout representation that enables native 3D floorplanning of complex-shaped 3D blocks, i.e., orthogonal polyhedra spread onto multiple dies. Furthermore, it can also be applied during 3D floorplanning of both rectangular and rectilinear 2D blocks. In the former case, experiments reveal superior estimated wirelength and packing density compared to previous work.