Design of Bit Error Rate Tester Based on a High Speed Bit and Sequence Synchronization

摘要

In traditional BER (Bit Error Rate) tester, bit synchronization applied digital PLL and sequence synchronization utilized sequence's correlation. It resulted in a low speed on bit and sequence synchronization. this paper came up new method to realize bit and sequence synchronization .which were Bit-edge-tracking method and Immitting-sequence method.The BER tester based on FPGA was designed.The functions of inserting error-bit and removing the false sequence synchronization were added. The results of Debuging and simulating display that the time to realize bit synchronization is less than a bit width, the lagged time of the tracking bit pulse is 1/8 of the code cycle,and there is only a M sequence's cycle to realize sequence synchronization.This new BER tester has many advantages,such as a short time to realize bit and sequence synchronization,no false sequence synchronization,testing the ability of the receiving port's error -correcting and a simple hareware.