A symbolic simulation-based methodology for generating black-box timing models of custom macrocells

摘要

We present a methodology for generating black-box timing models for lull-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simulation to explore the input arrival time space and determine the input arrival time windows that result in proper operation. This approach integrates symbolic timing simulation into existing static timing analysis flows and allows automated modelling of the timing behavior of aggressive lull-custom circuit design styles.