Pipelined Match-Lines and Hierarchical Search-Lines for Low-Power Content-Addressable Memories

摘要

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024 × 144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18μm CMOS process.