We develop a region-based timing characterization approach to detect hardware Trojans (HTs) on integrated circuits (ICs). In order to ensure the scalability of the approach, we partition the target IC into well-formed and non-overlapping regions and detect hardware Trojans on all circuit locations by examining the timing properties of the transistor paths. Based on the circuit partition, we insert a minimal number of test points that provide additional observation interfaces for the delay measurements of all circuit locations. Our evaluations on ISCAS and ITC benchmarks show that the region-based Trojan detection via test points can detect hardware Trojans accurately with well controlled area overhead and test time.
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