Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS

摘要

This paper presents a low-noise ΔΣ fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the ΔΣ fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6 GHz ΔΣ fractional-N PLL implemented in 65 nm CMOS exhibits nearly -100 dBc/Hz in-band noise contribution and -53 dBc in-band fractional spur performances from a 1.8 GHz carrier.