A novel energy-efficient serializer design method for gigascale systems

摘要

Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional differential cascode voltage switch is modified with pass-gate logic by replacing a PMOS load with a resistor load and adding an inductive peaking structure. Simulation results show that the proposed method reduces the power-delay-product by up to 70%, compared to the conventional current-mode-logic-based serializer.