Universal Numerical Encoder and Profiler Reduces Computing's Memory Wall with Software, FPGA, and SoC Implementations

摘要

Numerical computations have accelerated significantly since 2005 thanks to two complementary, silicon-enabled trends: multi-core processing and single instruction, multiple data (SIMD) accelerators. Unfortunately, due to fundamental limitations of physics, these two trends could not be accompanied by a corresponding increase in memory, storage, and I/O bandwidth. We describe Application Acceleration (APAX) numerical encoding, a computationally efficient, adaptive method that lowers the memory wall for high-performance computing (HPC) datasets. APAXI has been implemented in both software and hardware. On 24 HPC datasets, APAX achieved encoding rates between 3:1 and 10:1 without changing the dataset's statistical or spectral characteristics.