Benchmark analysis of AWGR-based optical tiled architectures for multi-socket HPC boards

摘要

We analyze the execution time and energy performance of tiled optical multi-socket HPC boards with all-to-all AWGR-based interconnection and with different optimizations techniques under PARSEC benchmarking traffic, and we compare it with a state-of-the-art electronic multi-socket architecture. Benchmark results show significant performance improvements and up to 2× energy saving when using dynamic variable bandwidth communication technique.