A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits

摘要

This paper proposes a built-in self-adjustment scheme to adjust pMOSFET and nMOSFET performances to their target values. Independent control of MOSFET performances can boost circuit performance without large leakage overhead. All-digital monitor circuits have been developed to detect pMOSFET and nMOSFET variations. The scheme has been fabricated in a 65 nm process. Measurement results from corner chips confirm the validity of the scheme. At 0.7 V operation, more than 50% of circuit speed degradation has been recovered. The proposed scheme achieves 2.6 times leakage saving than the conventional critical path delay based scheme. The scheme is suitable for typical-case design and yield enhancement.