An advanced CCD emulator with 32MB image memory

摘要

As part of the LSST sensor development program we have developed an advanced CCD emulator for testing newmultichannel readout electronics. The emulator, based on an Altera Stratix II FPGA for timing and control, produces 4channels of simulated video waveforms in response to an appropriate sequence of horizontal and vertical clocks. Itfeatures 40MHz, 16-bit DACs for reset and video generation, 32MB of image memory for storage of arbitrary grayscalebitmaps, and provision to simulate reset and clock feedthrough ("glitches") on the video channels. Clock inputs arequalified for proper sequences and levels before video output is generated. Binning, region of interest, and reverse clocksequences are correctly recognized and appropriate video output will be produced. Clock transitions are timestampedand can be played back to a control PC.A simplified user interface is provided via a daughter card having an ARM M3 Cortex microprocessor and miniaturecolor LCD display and joystick. The user can select video modes from stored bitmap images, or flat, gradient, bar, chirp,or checkerboard test patterns; set clock thresholds and video output levels; and set row/column formats for imageoutputs. Multiple emulators can be operated in parallel to simulate complex CCDs or CCD arrays.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.