Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers

摘要

In this work, two different methodologies for the implementation of a Fast Fourier transform processor: FFT using CORDIC and FFT using Multiplier are investigated. Reconfigurable FFT using radix-2 Decimation in frequency technique is chosen for the comparison. In terms of area and power, both the implementations were analyzed. Coordinate Rotation Digital Computer (CORDIC) is widely used in DSP applications. It utilizes only add and shift operations instead of multipliers. Both CORDIC and multiplier are employed here for twiddle factor multiplication. The experimental result shows that the multiplier based FFT implementation has lower area and power consumption, as compared to CORDIC based implementation.