In this paper we explore the area overhead associated with the stochastic assembly of nanoscale logic. In nanoscale architectures, stochastically assembled nanowire decoders have been proposed as a way of addressing many individual nanowires using as few photolithographically produced mesoscale wires as possible. Previous work has bounded the area of stochastically assembled nanowire decoders for controlling nanowire crossbar-based memories. We extend this analysis to nanowire crossbar-based logic and bound the area required to supply inputs to a nanoscale circuit via mesoscale wires. We also relate our analysis to the area required for stochastically assembled signal-restoration layers within nanowire crossbar-based logic.
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