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A low data rate FM-UWB transmitter with-based sub-carrier modulation and quasi-continuous frequency-locked loop

机译:具有基于子载波调制和准连续锁频环路的低数据速率FM-UWB发射机

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This paper describes the architecture and circuit design of a low data rate FM-UWB transmitter. A Δ-Σ fractional-N PLL with a multi-phase relaxation oscillator is designed to enable sub-carrier modulation with reduced quantization noise. The triangular waveform output of the relaxation oscillator directly modulates an LC VCO to have the UWB-compliant spectrum. The center frequency of the LC VCO is quasi-continuously tuned by a Δ-Σ DAC based frequency-locked loop with the power consumption of 1.1mW. The 3.43-4.03GHz FM-UWB transmitter implemented in 0.18μm CMOS consumes the total power of 9.6mW.
机译:本文介绍了低数据速率FM-UWB发射机的体系结构和电路设计。具有多相弛豫振荡器的Δ-Σ分数N PLL设计用于实现具有降低的量化噪声的子载波调制。张弛振荡器的三角波输出直接调制LC VCO,使其具有UWB兼容频谱。 LC VCO的中心频率由基于Δ-ΣDAC的锁频环准连续调谐,功耗为1.1mW。在0.18μmCMOS中实现的3.43-4.03GHz FM-UWB发射器消耗的总功率为9.6mW。

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