A Multiple Faults Test Generation Algorithm Based on Neural Networks and Chaotic Searching for Digital Circuits

摘要

A multiple faults test generation algorithm based neural networks for digital circuits is proposed in this paper because the test generation for multiple faults in digital circuits is more difficult. This algorithm change multiple faults into single fault firstly and constructs the constraint network of the fault for the single fault circuit with method of neural networks. The test vectors for multiple faults in the original circuit can be obtained by solving the minimum of energy function of the constraint network for the fault with chaotic searching method. The experimental results on some international standard circuits demonstrate the feasibility of the algorithm.