Reliable microprocessors for FPGAs: State of the art and trends

摘要

The need of critical applications has derived in the development of several techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. This article presents a state of the art in the techniques for reliable microprocessor architectures for FPGAs. One of this techniques, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR), allows the development of coarse grain modularity architectures where the redundant module is the soft-core microprocessor. However, its main lack is a suitable synchronization method for the faulty module. This paper shows the trends on synchronization methods and proposes the use of an Autonomous Fault Tolerant System (AFTS) for developing a more suitable synchronization method.