A novel forward error correction decoding structure for 10G/40G Ethernet

摘要

This paper presents a novel VLSI structure of frame boundary detecting system for 10G/40G Ethernet frame forward error correction layer as well as fast frame synchronous methodology. By changing the endian mode, the improved error trapper circuit can work in both syndrome generator mode and error trapper mode. So the frame boundary detecting speed is accelerated by detecting two frame boundaries at the same time, and the frame will be fast-synchronized. Experimental result shows that the frame synchronizing speed is twice of that of the conventional method, while the hardware overhead is very small. With the proposed method, the correct frame boundary can be detected by shifting 1055 times at most, while the conventional method needs 2111 times.