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A 驴5OdBc Spur 0.13驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture

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Notice of Violation of IEEE Publication Principles
A 驴5OdBc Spur 0.13驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture

机译：违反IEEE发布原则
使用多调节器体系结构的DBS卫星接收器SOC的驴5OdBc杂散0.13驴mm CMOS环形振荡器PLL

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Notice of Violation of IEEE Publication Principles

驴A -5OdBc Spur 0.13 驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture驴
by Maxim, A.; Poorfard, R.; Kao, J.;
in the Proceedings of the 2007 IEEE

机译：Maxim，A.违反DBA卫星接收器SOC的IEEE出版原则

驴A -5OdBc杂散0.13驴m CMOS环形振荡器PLL的通知，违反DBI卫星接收器SOC。 Poorfard，R .; Kao，J .;
在2007 IEEE会议论文集中

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《Radio and Wireless Symposium, 2007 IEEE》|2007年|P.427-430|共4页
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Maxim; A.; Poorfard; R.; Kao; J.;
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中图分类工业技术;
关键词
CMOS integrated circuits; attenuators; direct broadcasting by satellite; phase noise; radiofrequency filters; radiofrequency integrated circuits; radiofrequency oscillators; system-on-chip; television receivers; 0.13 mum; 10 kHz to 22.5 MHz; 3.3 V; 40 mA; CMOS ring o;

机译：CMOS集成电路;衰减器;卫星直接广播;相位噪声;射频滤波器;射频集成电路;射频振荡器;片上系统;电视接收器; 0.13μm; 10 kHz至22.5 MHz; 3.3 V; 40 mA; CMOS环形Ø;

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1. Notice of Violation of IEEE Publication PrinciplesA Low Reference Spurs 1–5 GHz 0.13 $mu$m CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter Architecture [J] . Maxim A. IEEE Journal of Solid-State Circuits . 2007,第11期

机译：违反IEEE出版原则的通知低参考杂散使用完全采样前馈环路滤波器架构的1-5 GHz 0.13美元/μmCMOS频率合成器
2. Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation [J] . Maxim A. IEEE Journal of Solid-State Circuits . 2005,第1期

机译：违反IEEE发布原则的通知使用模拟相位插值的0.16-2.55-GHz CMOS有源时钟去歪斜PLL
3. Notice of Violation of IEEE Publication PrinciplesA multi-rate 9.953-12.5-GHz 0.2-;C;m SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit [J] . Maxim A. IEEE Journal of Solid-State Circuits . 2006,第4期

机译：违反IEEE出版原则的通知使用电阻调谐变容二极管和电源推动消除电路的多速率9.953-12.5-GHz 0.2-; C; m SiGe BiCMOS LC振荡器
4. A 驴5OdBc Spur 0.13驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture [C] . Maxim, A., Poorfard, Radio and Wireless Symposium, 2007 IEEE . 2007

机译：使用多调节器架构的DBS卫星接收器SOC的驴5OdBc杂散0.13驴CMOS环形振荡器PLL
5. Notice of Violation of IEEE Publication Principles: An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors [O] . Salman Onsori, Arghavan Asad, Kaamran Raahemifar, 2019

机译：违反IEEE出版物原则的通知：未来暗硅嵌入式芯片 - 多处理器的节能异构内存架构

Notice of Violation of IEEE Publication PrinciplesA 驴5OdBc Spur 0.13驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture

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Notice of Violation of IEEE Publication Principles
A 驴5OdBc Spur 0.13驴m CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture