VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel

摘要

By implementing an FPGA-based simulator, this paper investigates the semi-random construction of high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Then a new QC-LDPC decoder hardware architecture is proposed. Finally, a read channel signal processing datapath consisting of a parallel Max-Log-MAP detector and the proposed QC-LDPC decoder is implemented in 0.13 mum CMOS. This design achieves a throughput up to 1.8Gbps under 16 iterations of LDPC decoding