This paper presents a high-speed subtractor in residue number system (RNS). In this paper, utilizing the conversion of single range unsigned (SRU) number system to single range signed (SRS) number system, we have made the subtraction more rapidly. Moduli set of (2n - 1, 2n, 2n + 1) is very attractive and has so many advantages over the other moduli sets, when realizing the related circuits. Beside the arithmetic operation delays are restricted by modulo 2n + 1. Therefore, this method especially for above moduli will be very useful. By this fact, n + 1 bit wide subtractors are reduced to n bit wide subtractor. It is shown that the proposed design delay is about n/(n + 1) percent of existing one. This property has lead to more efficient realization of VLSI aspects
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机译：本文提出了一种残差数系统（RNS）中的高速减法器。在本文中，利用单范围无符号（SRU）编号系统到单范围有符号（SRS）编号系统的转换，我们使减法运算更加迅速。 （2 n -1，2 n ，2 n + 1）的模数集非常吸引人，并且与其他模数相比具有很多优势在实现相关电路时进行设置。除了算术运算延迟外，还受模2 n +1的限制。因此，此方法（特别是用于以上模数的方法）将非常有用。由于这个事实，n + 1位宽的减法器被减为n位宽的减法器。结果表明，建议的设计延迟约为现有延迟的n /（n +1）％。此属性导致更有效地实现VLSI方面
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