The new method proposed in this paper considers the dynamic, static and short-circuit power dissipation simultaneously for making a comprehensive, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, the method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for a VLSI chip, two illustrative cases are observed. Finally, the future works are discussed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.
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