As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires grow rapidly, and have a significant impact on power consumption and signal integrity of an integrated circuit. As buses are major components of a design, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance. In this paper, we address the problem of using Hamming single error correcting code by optimizing both wire permutation and spacing. We propose an efficient polynomial time algorithm which applies graph theory for this optimization problem. Unlike previous studies [17], our approach can be applied to high bandwidth fault-tolerant buses to efficiently reduce the coupling capacitances by utilizing available space. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs for evaluating energy reduction. The results show that our approach can save energy up to 43% for the best case, and30% for the worst with 20 x dmin (min is the mininal permitted wire distance) additional width on RLC model. Besides, we also provided comprehensive comparisons in experimental result section for different fault-tolerant bus layout methods and error correction codes.
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机译：随着技术缩小到纳米尺寸，相邻总线之间的耦合电容迅速增长，并对集成电路的功耗和信号完整性产生重大影响。由于总线是设计的主要组成部分，因此设计容错总线在降低功耗的同时提高可靠性而又不牺牲性能是很重要的。在本文中，我们通过优化导线排列和间距来解决使用汉明单纠错码的问题。我们提出了一种有效的多项式时间算法，该算法将图论应用于此优化问题。与先前的研究[17]不同，我们的方法可以应用于高带宽容错总线，以通过利用可用空间来有效地减少耦合电容。对于我们的实验，我们使用了从12个SPEC2000基准程序获得的指令总线轨迹来评估节能效果。结果表明，我们的方法在20 x d min （ min 是RLC模型上的最小允许导线距离）附加宽度。此外，我们还在实验结果部分对不同的容错总线布局方法和纠错码进行了全面的比较。
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