Efficient FFT processor is one of the key components in the implementation of wideband multicarrier communication systems. As programmable logic device (PLD) technology have been developing fast, some large-scale implementation of FFT processor in one FPGA becomes possible. This paper compares the finite word length effect of the decimation in time (DIT) and decimation in frequency (DIF) algorithm, and simplifies the complex multiplication operation in the design of the FFT structure for more general case in which the FFT point is only power of two rather than four. It gives the theoretical delay in one type proposed structure for multicarrier system which is variable point for more general case in which utilization can be raised to 100%. Finally, an efficient FFT processor with system clock 40 MHz and delay 2.7 mus has been implemented in the ALTERA APEX20K-200 hardware platform. It has been analysed and tested to validate its capability in order to meet the need of wideband multicarrier communication system such as IEEE.802.11a
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