A technique for modular design of self-checking carry-select adder

摘要

The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing self-checking carry-select adders set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0.5/spl mu/m CMOS technology. The area needed for implementing the self-checking adders is 16.07 % to 20.67% more than that required in adders without built-in self-checking capability.