Functional block extraction is a useful tool for layout verification of integrated circuits. In particular, it facilitates the network comparison problem by transfering it to a higher level of hierarchy. This paper describes a computer program called BLEX (Block Extractor), which is able to extract any given circuit block, e.g., gates, flip-flops, memory cells, differential amplifiers, darlington circuits etc., from a SPICE-like network description. The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions. Descriptions of the functional blocks having the same format as the network description are supplied by the user. The circuit to be examined results usually from a preceding circuit extraction. The extractor and BLEX are part of the layout verification system ALAS (A Layout Analysis System).
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