An MOS Digital Network Model on a Modified Thevenin Equivalent for Logic Simulation

摘要

A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.