A NOVEL COMPONENT MODEL FOR THE SYNCHRONOUS DATAFLOW PARADIGM

摘要

A novel component model for component-based embedded systems based on the dataflow paradigm is presented. This model allows design accompanying analysis of many interesting questions regarding deadlock detection, memory usage, cyclic schedules, and protocol compatibility. One objective of this model is to detect as many component errors during design as possible. Moreover, this model is compositional resulting in well-defined hierarchical abstraction. Altogether, this results in more reliable development of complex applications in a shorter design time.