An Efficient, Optimized JPEG2000 Tier-1 Coder Hardware Implementation

摘要

It is a well-known fact that the major bottleneck of a JPEG2000 encoder is the bit/context modeling and arithmetic coding tasks (also known together as the tier-1 coding portion of EBCOT). Whereas the technique of using multiple coding passes on multiple bit-planes follows a near-optimal path on the rate-distortion curve and helps create an elegant embedded codestream, this tier-1 coding requires a large amount of computation for each block of data as well as significant memory resources and memory accesses. Luckily, the JPEG2000 standard allows us to perform a number of the tier-1 coding tasks in parallel. If this parallelism is exploited and if smart data organization techniques are used, then the throughput of a JPEG2000 system can be dramatically improved. This paper discusses an efficient, optimized hardware implementation of a tier-1 coder that exploits these available parallelisms. This paper also describes implementation on Xilinx FPGA platforms. The proposed technique described in this paper is approximately 50% faster than the best technique described in the literature.