The purpose of this paper is to present a methodology for rapid prototyping of biorthogonal wavelet transforms on FPGAs. The methodology is based on adequate partitioning of a time interleaved "wait cycles" free architecture. The design has been captured using a schematic capture tools and can be parameterised in terms of the number of filter coefficients, data and coefficient word-lengths, digit size and degree of pipelining. The efficiency of the approach has been verified on the Xilinx 4000 FPGA series.
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