In this paper, we present a comprehensive high-level synthesissystem that is geared towards reducing power consumption in control-flowintensive circuits. An iterative improvement algorithm is at the heartof the system. The algorithm searches the design space by handlingscheduling, module selection, resource sharing and multiplexer networkrestructuring simultaneously. The scheduler performs concurrent loopoptimization and implicit loop unrolling. It minimizes the expectednumber of cycles of the schedule without compromising on the minimum andmaximum schedule lengths. A fast simulation technique based on tracemanipulation aids power estimation in driving synthesis in the rightdirection. Experimental results demonstrate power reduction of up to 85%with minimal overhead in area over area-optimized designs operating at 5V
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