High Performance superscalar computer processors use a technique known as "register renaming" to facilitate out-of-order instruction execution. Most of these processors support instruction set architectures with multiple data sizes. Register renaming in such processors can be made much more effective and a performance improvement may be gained by implementing a technique we call sectored renaming. The improvement comes from the increased level of renaming for the same number of registers and from the reduction in the memory access critical path due to the elimination of the alignment network. In this paper the authors present the sectored renaming design technique and demonstrate experimentally as much as 8% performance improvement on SPEC95 benchmarks.
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