Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter

摘要

In this paper a new interconnect capacitance measurement method with a sub-attoFarad (>10/sup -18/ F) resolution is presented. We have developed a SPD (Single Pattern Driver) which allows to obtain directly all the coupling terms for a system of several interconnect electrodes. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 /spl mu/m CMOS process with low-k. Moreover, we demonstrate that this SPD can be used for process characterisation and monitoring, and extraction tool validation.