1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder

摘要

This paper reports 1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI. Using BDLCT, the maximum operating frequency of a digital quadrature modulator is 482 MHz at 5 V and 68 MHz at 1.5 V. Compared to the circuit without BDLCT, the 12-bit delay time of a 16-bit adder with BDLCT is improved by 56% at 1.5 V.