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High-performance implementation of convolution on multiple field-programmable gate array boards using number theoretic transforms defined over the Eisenstein residue number system

机译:使用在爱森斯坦残数系统上定义的数论变换,在多个现场可编程门阵列板上进行卷积的高性能实现

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Abstract: Fast implementation of convolution and discrete Fourier transform computations are frequent problems in signal and image processing. These operations typically use fast Fourier transform (FFT) algorithms. Number Theoretic Transforms (NTTs) over a finite group of primes can also be used for this purpose. Using the NTT over Fermat primes (2$+q$/ $PLU 1) in field programmable gate array (FPGA) designs is advantageous, because the arithmetic can be efficiently and fast realized. By using Fermat primes, all multiplications, which have a O(q$+2$/) area requirement, can be replaced by a q $YLD q (rotation) shift operation, which has only a O(q$DOT@log(q)) area requirement. The area requirement reduces to O(q) for a fully pipelined realization with hardwired shifts. Using the Eisenstein Residue Number System (ERNS), which defines complex number over the polynom j$+2$/ $PLU j $PLU 1 $EQ 0, instead of j$+2$/ $PLU 1 $EQ 0 for Gaussian integers, gives the additional advantage that the transform length is extended from q to 6q by only one addition for each complex multiplication. An RNS-based multiple FPGA-board implementation is presented which demonstrates both the performance and packaging advantages of the new ERNS-FPGA- NTT paradigm.!20
机译:摘要:卷积的快速实现和离散傅立叶变换计算是信号和图像处理中的常见问题。这些操作通常使用快速傅立叶变换(FFT)算法。有限质数组上的数论变换(NTT)也可以用于此目的。在现场可编程门阵列(FPGA)设计中使用Fermat素数(2 $ + q $ / $ PLU 1)上的NTT是有利的,因为可以高效,快速地实现该算法。通过使用费马素数,所有具有O(q $ + 2 $ /)面积要求的乘法都可以由aQ $ YLD q(旋转)移位运算代替,后者仅具有O(q $ DOT @ log(q) ))面积要求。对于具有硬连线移位的完全流水线实现,面积要求降低为O(q)。使用爱森斯坦残数系统(ERNS),该系统定义多项式j $ + 2 $ / $ PLU j $ PLU 1 $ EQ 0的复数,而不是j $ + 2 $ / $ PLU 1 $ EQ 0的高斯整数给出了额外的优点,即对于每个复数乘法,变换长度从q扩展到6q仅需进行一次加法运算。提出了一种基于RNS的多FPGA板实现,展示了新型ERNS-FPGA-NTT范例的性能和封装优势。20

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