Optical receivers for smart-pixel a

摘要

Abstract: Proposals to use large amounts of optics inside complex digital systems such as switches and computers impose new opportunities and new constraints on the optical receiver to be used. Since the receiver may exist on the chip with the VLSI, constraints on layout area and power consumption are severe. Since the system may be local in nature, the use of multiple-beam receivers may be possible. Finally, locality also implies that timing information may be available, permitting the use of synchronous sense-amplifier-based optical receivers. Issues associated with these points are discussed as they relate to several different examples of smart- pixel receivers. Results include high-impedance FET-SEED optical receivers with 3 mW power consumption and 1 Gb/s operation, hybrid-CMOS (0.8 micrometer) transimpedance receivers operating at roughly 200 fJ/bit at 1 Gb/s and below 10 fJ/bit at 311 Mb/s consuming 8 mW, and sense-amplifier circuits consuming about 1 mW at 330 Mb/s and 100 fJ/bit. !24