Direct digital synthesis has the major advantage that the low phase noise of the (quartz) reference oscillator can be transferred directly to the signal output. However, limitations on the precision of the high speed Digital to Analogue Converter (DAC) required to generate the output waveform cause a high level of spurious signals to be generated. The paper describes a simple spurious signal reduction method which can be applied to the output of a high frequency programmable rate multiplier. The advantage of the rate multiplier method of direct frequency synthesis is that no high speed DAC is required. The method extracts a phase error signal in the form of analogue samples directly from the rate multiplier signal. This signal is used in a novel self adjusting delay compensation circuit (SADC) to correct the time positions of the transitions of the square wave output waveform. This has the effect of reducing both the spurious components and the broadband phase noise of the signal. Also described is a method of converting the waveform from any frequency source into a form suitable for the application of the SADC. This method allows SADCs to be applied in cascade for progressive reduction of phase noise.
展开▼
