A pipelining fuzzy inference chip with a self-tunable knowledge base is presented in this paper. Up to 49 rules are inferred in parallel in the chip, and the memory size of its knowledge (rule) base is only 84 bytes since the memory-efficient and adjustable fuzzy rule format as well as the dynamic rule generating circuits are used. Based on these mechanism and a rule weight tuner, the possibility of narrowing, widening, moving,amplifying, and/or dampening the membership functions is provided in it, and makes the inference process self-adaptive. A three-stage pipeline in the parallel inference architecture makes the chip very fast. It can yield an inference rate of 467 K inferences/sec operating at a clock rate of 30 MHz.
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