A systolic array for neural network implementation

摘要

The implementation of a multilayer perceptron, based on a linear array of interconnected processing elements (PEs), is described. An iterative formulation of the network model is presented and the mapping with the computing architecture is derived. A preliminary version of the proposed algorithm has been implemented on the APx Accelerator, a parallel processor system using a proprietary VLSI (the ACIIM chip). The efficiency of the approach is considered for real-time systems, where the general-purpose programming model allows the APx to run the neural model and other processing tasks required by the application.