A multistage half-band FIR (finite impulse response) decimator has been implemented on a 40000-gate, 1.5- mu m CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). The filter handles 20-b, 2.56-M sample/s input data. It has been tested for frequency shifting and zooming in a prototype FFT (fast Fourier transform) spectrum analyzer and has increased the frequency resolution by up to 2/sup 17/ times without aliasing, resulting in frequency resolution on the order of 20 mHz; it has a 96-dB dynamic range.
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机译:多级半频段FIR(有限脉冲响应)放样器已经在40000栅极,1.5 - MU M CMOS阵列上实现,其以25.6 MHz的时钟速率(2.56 MHz的采样率)消散1.5W。过滤器处理20-B,2.56-M个采样输入数据。它已经测试了在原型FFT(快速傅里叶变换)频谱分析仪中的频率移位和变焦,并且在没有混叠的情况下增加了多达2 / SUP 17 /次的频率分辨率,导致频率分辨率为20 MHz。它具有96-dB动态范围。
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