In many cases, it may be possible to redesign parallel algorithms so as to provide a low-cost online scheme for hardware error detection without any hardware modifications. This approach is called algorithm-based error detection. Two useful computations in signal processing are analyzed: QR factorization and singular-value decomposition. For each of these applications, numerous ways of applying algorithm-based error detection using different system-level encoding strategies are investigated. Different schemes have been observed to result in varying error coverages and time overheads. The results of studies performed on a 16-processor Intel iPSC-2/D4/MX hypercube multiprocessor are reported.
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