A discussion is presented as to why the present approach to cache architecture design results in unpredictable performance improvements in real-time systems with priority-based preemptive scheduling algorithms. The SMART cache design is shown to be compatible with the goals of scheduling in a real-time system. The results of this research provide a scheme not only for utilizing the performance enhancement provided by hierarchical memory designs, but also for fine tuning these enhancements to provide increased benefit to the desired scheduling goal.
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