A Sub-μW Power 10 bit ΔΣ ADC for Biomedical Applications

摘要

We present a sub-μW power consumption ΔΣ ADC with a target 10 bit resolution for biomedical application. A fully passive loop filter based CTDSM was first realized followed by a digital comb LPF and decimator. The loop filter employs an asynchronous NRZ DAC and a feedforward summing enabled comparator realization. We propose a low power architectural implementation of a digital comb filter. The low power operation is enabled at the architectural level due to the novel clock enabled adder based comb filter. Further, a proposed pass gate and keeper based full adder circuit implementation is used for sub-μW power consumption. The design was realized in a standard 180 nm CMOS mixed mode technology in Semiconductor Laboratory (SCL), India. Simulation results show a power consumption of 920 nW for the ΔΣ ADC for a 10 kHz biomedical bandwidth.