Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links

摘要

In this work, alternatives to implement 8b/10b encoders in FPGAs for serializer-deserializer links are evaluated. Custom implementations based on decoders and look-up tables are benchmarked, and then compared against an implementation based on a commercial IP. The evaluation is performed in terms of area, power consumption, timing margins, and required resources. The used hardware is a Kintex-7 evaluation board with an external 600 MHz clock reference, where a basic transceiver including scramblers, the encoders, and a serializer/deserializer was implemented. Results show that custom implementations are much more compact and consume less than 50% of power in comparison to the IP-based implementation per lane usage, at the cost of reduced functionalities.