A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends

摘要

High resolution commercial radars which feature arrays of transmit and receive antennas and that rely on unambiguous range-Doppler signal processing with hard real-time constraints require fast memories to store intermediate results. Typical radar data matrices can occupy up to a gigabyte of space. A custom DRAM controller tailored for digital radar back ends and software-defined radars is presented. It is implemented on an FPGA and supports data buffering between the two FFT stages inside a two-dimensional spectral analysis system. In parallel, it allows the remaining part of the SDRAM to be used as a virtual FIFO buffer for the output results. Experimental tests have shown that when both pairs of the proposed memory controller's ports are accessed simultaneously, their joint data throughput is within 10% of the gross theoretical limit for the utilized DDR3 module.