A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback

摘要

Dynamic domino circuit affords significant advantages in speed performance and area by virtue of dynamic operating behavior and un-complementary circuit structure, while compromising too much power consumption and noise tolerance. In this paper, a highspeed full adder based on dynamic domino circuit is proposed by utilizing the DICG (Delayed-Inverted-CLK-Gating) positive feedback scheme. Thanks to the DICG technique, it relaxes the competition between pull-up and pull-down networks effectively, achieving notable improvements in speed, power dissipation and circuit stability. Experimental results show that the presented dynamic domino adder exhibits 21.2% improvement in speed performance and 18.7% reduction in power-delay product compared with previous work when using a TSMC 65nm process technology.